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JRE detects
EXCEPTION_ACCESS_VIOLATION
when trying to use Verilator as Chiseltest's backend
#649
opened Jun 25, 2023 by
hiroshi-ya
poke
in ChiselScalatestTester
occurs on falling clock edge in traces
#646
opened Jun 19, 2023 by
yupferris
TODO: implement plusarg intrinsic support for all supported simulators and formal verification
#638
opened Jun 9, 2023 by
ekiwi
Feature request: Always advance clock by one cycle at the end of failed tests
#516
opened Apr 14, 2022 by
KasperHesse
feature request: PSL support for formal verification.
feature request
#416
opened Oct 21, 2021 by
Martoni
Feature request - cache elaboration across tests
feature request
#380
opened Aug 18, 2021 by
oharboe
TopLevel output port cannot have inferred width if testing with verilator
bug
Something isn't working
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