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Issues: chipsalliance/chisel
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Calling .asUInt on a Bool returns the Bool itself (rather than a true UInt)
#4163
opened Jun 11, 2024 by
jackkoenig
Calling .pad on Bool results in requirement failure with no explanation
#4162
opened Jun 11, 2024 by
jackkoenig
Boring to a FlatIO Port does not properly terminate at the port -- descends into the module
#4155
opened Jun 7, 2024 by
mwachs5
Provide suggestName to Queue(and other Chisel Library Moduels)
#4055
opened May 5, 2024 by
sequencer
Hard to obtain needed context to build IR for referencing results of
FirrtlMemory
#4022
opened Apr 22, 2024 by
SpriteOvO
Pass Chisel information to firtool to generate debug information for the Tywaves project
#4015
opened Apr 19, 2024 by
rameloni
4 tasks
[Feature Request/Proposal] Upstream Utils from rocket-chip into chisel where applicable.
#3954
opened Mar 27, 2024 by
lordspacehog
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