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HC32: Update Clock Configuration #27099
base: bugfix-2.1.x
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I see… Since #define F_HCLK 200000000 // 200MHz HCLK
#define F_CPU F_HCLK |
I pushed a commit with what makes sense to me, but of course please apply corrections and clarifications. It's interesting that HC32 clock frequency is so configurable, and it will be cool to be able to change the clock speed by changing a single define. |
I think i've got an idea how most of the clock configuration can be handled automagically at compile time, with validation and everything. PLL config seems a bit daunting to make automatic, so i'll put that off for now :D I'll push a commit tomorrow, gotta test this first.
Yeah, it's kinda weird how capable and configurable this MCU actually is. But then there's also some really weird additions, like two independent watchdog timers... Anyway, it's a really interesting if not weird chip |
Thanks for the feedback, looking forward to your update! |
So, i've pushed a commit to automatically handle everything related to the clock configuration using defines in PLL config was indeed fairly daunting, but i did manage to pull it off - at least kind of. Maybe someone whos a bit more skilled in C++ could take a look ? |
Description
Undoes some changes made in in #27086 and updates some comments to reflect the clock architecture on HC32.
Also see #27086 (comment).
With feedback in comments, this PR now also includes a more general overhaul of the HC32 HAL's clock configuration.
HC32 Clock Architecture
This part is meant to provide a high-level overview of the clock architecture used in the HC32 HAL, and how it is configured in Marlin.
In the HC32 HAL, all clocks are derived from the
MPLL-P
clock, divided by a fixed divider.First, the MPLL input clock is set to one of three sources:
BOARD_XTAL_FREQUENCY
== 8 MHz)BOARD_XTAL_FREQUENCY
== 16 MHz)The MPLL then locks onto the input clock divided by an internal division factor
M
.The resulting clock is then multiplied by internal factor
N
, before beign divided by factorsP
,Q
andR
to create the equally named output clocks (MPLL-P
,MPLL-Q
andMPLL-R
).MPLL-Q
andMPLL-R
are not used by the HC32 HAL, so can be ignored.These values are configured in the
pllConf
struct.(Final
MPLL-P
output clock is calculated as $ f_{P} = \frac{\frac{f_{in}}{M} * N}{P} $.)The
MPLL-P
clock is then divided by the dividers configured in thesysClkConf
struct to get the final output clocks.For example,
HCLK = MPLL-P / 1
andPCLK2 = MPLL-P / 8
.To ensure all clocks are valid, they are verified using the
assert_system_clocks_valid
function (when available).See Fig. A for a marked up clock system block diagram highlighting the path of the various clocks used in the HC32 HAL.
Also consider referencing Section 4.2.1 of the HC32F460 Reference Manual if more information is needed.
Requirements
HC32-based printer
Benefits
Updates documentation for HC32 HAL clock configuration.
Configurations
N/A
Related Issues
N/A
Attachments