Is tranif0/tranif1 support on the roadmap?

[NickOveracker]

I'm working on a Verilog export functionality for a CMOS stick diagram tool, and the unidirectional nmos/pmos primitives won't do the job well. I want it to be compatible with iverilog because it's free and cross-platform, and I would prefer directing users to tools like this rather than some massive monolith like ModelSim.

If supporting tranif0/tranif1 is on the roadmap, I might be able to throw a few hours at it someday. I would just need to get caught up on why it's been difficult to implement up until this point so I can go in prepared.

[martinwhitaker]

Support for tranif devices was added in 2008, and there are tests in the test suite that use them. What do you think is missing?

[NickOveracker]

Per the project README's "Unsupported Constructs" section:

tran primitives, i.e. tran, tranif1, tranif0, rtran, rtranif1, and rtranif0 are not supported.

I found that section after noticing that tranif constructs do not work for multi-stage circuits.

For example, the following works:

module tranif_nor(a, b, y);
   input a, b;
   inout y;
   wire vdd, vss;

   assign vdd = 1;
   assign vss = 0;

   wire w1;

   // NOR
   tranif0(w1, vdd, a);
   tranif0(y, w1,  b);
   tranif1(y, vss, a);
   tranif1(y, vss, b);
endmodule

A simple testbench gives the expected results:

VCD info: dumpfile Sim.vcd opened for output.
         0 a=0 b=0 Y=1
        10 a=0 b=1 Y=0
        20 a=1 b=0 Y=0
        30 a=1 b=1 Y=0
tranif_nor_test.v:18: $finish called at 40 (1s)

But adding another layer of transistors to turn it from a NOR to an OR fails:

module tranif_or(a, b, y);
	input a, b;
	inout y;
	wire vdd, vss;

	assign vdd = 1;
	assign vss = 0;

	wire w1, w2;

	// NOR
	tranif0(w1, vdd, a);
	tranif0(w2, w1,  b);
	tranif1(w2, vss, a);
	tranif1(w2, vss, b);

	// OR
	tranif0(y, vdd, w2);
	tranif1(y, vss, w2);
endmodule

Yielding the following output:

VCD info: dumpfile Sim.vcd opened for output.
         0 a=0 b=0 Y=x
        10 a=0 b=1 Y=x
        20 a=1 b=0 Y=x
        30 a=1 b=1 Y=x
tranif_or_test.v:18: $finish called at 40 (1s)

I suppose the issue might be that it isn't possible to use tranif with a wire on the control signal. But it works just fine with nmos and pmos, so unless the gate has different requirements there I don't understand the problem:

module tranif_or(a, b, y);
	input a, b;
	inout y;
	wire vdd, vss;

	assign vdd = 1;
	assign vss = 0;

	wire w1, w2;

	// NOR
	pmos(w1, vdd, a);
	pmos(w2, w1,  b);
	nmos(w2, vss, a);
	nmos(w2, vss, b);

	// OR
	pmos(y, vdd, w2);
	nmos(y, vss, w2);
endmodule

VCD info: dumpfile Sim.vcd opened for output.
         0 a=0 b=0 Y=0
        10 a=0 b=1 Y=1
        20 a=1 b=0 Y=1
        30 a=1 b=1 Y=1
mos_or_test.v:18: $finish called at 40 (1s)

[martinwhitaker]

The README is very much in need of updating.

Regarding your OR function. The LRM does not define the behaviour of a tranif when the control input is undefined (x or z), so vvp chooses to follow the rules for MOS switches. The tranif is bidirectional, so if w1 or w2 ever gets assigned a L or H value, that can feed back onto the vdd and vss signals. You should be able to fix this by changing vdd and vss to have supply strength, but there does seem to be a bug in vvp that prevents y being updated at the right time.

Two other simulators I tried gave the same results as vvp for your original code, and gave the desired result once vdd and vss were changed to supplies.

[NickOveracker]

Supply strength - that helps!

Later today I'll go ahead and open an issue with the timing problem if you haven't already.